Many electronic products are based on embedded microprocessor systems. Embedded systems typically run an application specific program (firmware) that is resident in factory installed memory. This memory is often mask read only memory (mask ROM) or erasable programmable read only memory (EPROM). System performance is often limited by how fast a central processing unit (CPU) can fetch instructions from this ROM or EPROM code memory. This ROM or EPROM has slower access times than expansion memory units that are presently available.
Prior solutions to embedded system performance problems include adding instructions caches for the CPU. These instruction caches are small buffer memories contained within the CPU or adjacent to the CPU. Caches can be made larger to improve performance, but large caches are costly. Ultimately, the embedded system is still performance limited by the speed of instruction memory during cache-misses and the system resource contention that results.
Another prior solution to embedded system performance problems involves using fast memory (such as SRAM, DRAM, or SDRAM) for instruction memory. Currently, all fast memory types are volatile, so some method must be provided to reload the application program (firmware) or the memory must be non-corruptible. Reloading the application program requires that a copy be provided in either mask ROM or through an I/O interface with the additional requirement of what is commonly known as "boot-ROM." Though not considered embedded systems, personal computers operate using a combination of these techniques. These techniques are typically not used in embedded controllers because of the additional cost and complexity of I/O interfaces. Without the ability to reload the application program, the volatile memory must be made non-corruptible after it has been programmed in the factory during manufacture. This requires battery backup which is costly and limits product life. Also, the program can become corrupted, such as by electrostatic discharge or by alpha particles.
It is known to provide plug-in memory receptacles in printers and other electronic devices to permit a customer to add extension memory. This memory is used for-additional data buffering. See, for example, U.S. Pat. No. 5,137,379 to Ukai et al. (incorporated herein by reference). The Ukai et al. patent discloses a printer including a cartridge mounted read only memory. The cartridge contains memory devices for storing data for at least one character font set and for storing the printing operation control program. The print operation control program and character font set data can be set by connecting an appropriate cartridge to the main body of the printer. The specifications for a printer can be changed to suit a host machine by merely changing a cartridge.
U.S. Pat. No. 5,332,320 to Ohara (incorporated herein by reference) discloses a printing apparatus with mode selection. A printing apparatus includes a ROM in which various programs are stored. A separate detachable ROM cartridge can be inserted into a slot. The cartridge includes an emulation executing unit and an emulation judgement unit. An emulation mode is selected automatically by inserting the emulation mode external memory cartridge.
With respect to printers, ROM is included which stores executable code for performing various functions. The printers are coupled to computers, such as personal computers, directly or via a network. A computer sends a page description language, such as PCL or PostScript to the printer. The executable code in the printer interprets or decodes the page description language to render an image on a page. This involves scaling of fonts, drawing lines (vectors), filling areas with patterns, combining page content with pre-existing forms or watermarks, etc. The interpretation of the page description language can also involve possible rotation or clipping of graphics and resolution conversions and enhancement. The interpretation of the page description language can also involve dithering (gray scaling) for images.
Certain printers, such as those available from the assignee of the present invention, have programmable memory controllers. These memory controllers provide for selectively changing an address map, indicating the location of code to be executed, even while the code is being executed.